AK4343 Datasheet, PDF (32/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
„ System Reset
Upon power-up, the AK4343 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The initialization
cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are
internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is
complete.
„ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 17). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4343 in master mode, but must be input to the AK4343 in slave mode.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit SDTI (DAC)
BICK
0
DSP Mode
≥ 32fs
1
LSB justified
≥ 32fs
0
MSB justified
≥ 32fs
1
I²S compatible
≥ 32fs
Table 17. Audio Interface Format
Figure
Table 18
Figure 28
Figure 29
Figure 30
Default
In modes 1, 2 and 3, the SDTI is latched on the rising edge (“↑”) of BICK.
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18).
DIF1
0
DIF0
0
MSBS
0
0
1
1
BCKP
0
1
0
1
Audio Interface Format
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the rising edge (“↑”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the falling edge (“↓”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd falling edge (“↓”) of the
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd rising edge (“↑”) of the
BICK after the rising edge (“↑”) of LRCK..
Table 18. Audio Interface Format in Mode 0
Figure
Figure 24 Default
Figure 25
Figure 26
Figure 27
MS0478-E-01
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2006/10