AK4343 Datasheet, PDF (5/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
PIN/FUNCTION
No. Pin Name
I/O
Function
1 TEST1
-
Test 1 Pin
This pin should be left floating.
2 VCOM
O
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of DAC outputs.
3 AVSS
- Analog Ground Pin
4 AVDD
- Analog Power Supply Pin
5 ^VCOC
O
Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available)
This pin should be connected to AVSS with one resistor and capacitor in series.
RIN3
I Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
6 I2C
I
Control Mode Select Pin
“H”: I²C Bus, “L”: 3-wire Serial
7 PDN
I
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
8 ^CSN
CAD0
I Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode)
I Chip Address 1 Select Pin (I2C pin = “H”: I²C Bus Mode)
9 ^CCLK
SCL
I Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode)
I Control Data Clock Pin (I2C pin = “H”: I²C Bus Mode)
10 ^CDTI
SDA
I Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode)
I/O Control Data Input Pin (I2C pin = “H”: I²C Bus Mode)
11 SDTI
I Audio Serial Data Input Pin
12 TEST2
-
Test 2 Pin
This pin should be left floating.
13 LRCK
I/O Input / Output Channel Clock Pin
14 BICK
I/O Audio Serial Data Clock Pin
15 DVDD
- Digital Power Supply Pin
16 DVSS
- Digital Ground Pin
17 MCKI
I External Master Clock Input Pin
18 MCKO
O Master Clock Output Pin
19 SPN
O Speaker Amp Negative Output Pin
20 SPP
O Speaker Amp Positive Output Pin
21 HVDD
- Headphone & Speaker Amp Power Supply Pin
22 HVSS
- Headphone & Speaker Amp Ground Pin
23 HPR
O Rch Headphone-Amp Output Pin
24 HPL
O Lch Headphone-Amp Output Pin
25 MUTET
O
Mute Time Constant Control Pin
Connected to HVSS pin with a capacitor for mute time constant.
26
ROUT
RCN
O Rch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
O Receiver-Amp Negative Output Pin (RCV bit = “1”: BTL output)
27
LOUT
RCP
O Lch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
O Receiver-Amp Positive Output Pin (RCV bit = “1”: BTL output)
28 ^MIN
LIN3
I Mono Signal Input Pin (AIN3 bit = “0”: PLL is available)
I Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
29
RIN2
IN2−
I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
I Rch Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
30
LIN2
IN2+
I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
I Rch Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
31
LIN1
IN1−
I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
I Lch Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
32 ^RIN1
IN1+
I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
I Lch Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3) should not be left floating.
Note 2. AVDD or AVSS voltage should be input to I2C pin.
MS0478-E-01
-5-
2006/10