AK4650 Datasheet, PDF (70/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ Warm Reset
The AK4650 initiates warm reset process by receiving a single pulse on the SYNC. The AK4650 clears PR4 bit and PR5
bit in the Power-down Control Register. However, warm reset does not influence PR0-3, 6 and 7 bits in Power-down
Control Register.
Note 43. SYNC signal should synchronize with BITCLK after AK4650 starts to output BITCLK clock.
Note 44. If an external clock is used, external clocks should be supplied before issuing a sync pulse for warm reset. ADC
and DAC require 1028TS for the initialization.
Tsync_high Tsync2clk
SYNC
VIH
BITCLK
■ Active Test Mode
Figure 55. Warm Reset Timing
RESETN
VIH
SDATAOUT
SDATAIN
BITCLK
Tsetup2rst
VIH
HI-Z
Tof f
Figure 56. Activate Test Mode Timing
Note 45. All AC-link signals are normally low through the trailing edge of RESETN. Bringing RESETN high for the
rising edge of SDATAOUT causes the AK4650 AC-link outputs to go high impedance which is suitable for ATE
in circuit testing. Note that the AK4650 enters in the ATE test mode regardless SYNC is high or low.
Note 46. Once test modes have been entered, the only way to return to the normal operating state is to issue “cold reset”
which issues RESETN = “L” to “H” with both SYNC and SDATAOUT “L”.
MS0502-E-01
- 70 -
2007/04