AK4650 Datasheet, PDF (18/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ Timing Diagram
MCKI
BITCLK
1/Fmclk
VIH
VIL
Tmclkh
Tmclkl
Dmclk = Tmclkh x Fmclk x 100
= Tmclkl x Fmclk x 100
Figure 3. Master Clock Timing
Tbclk = 1/Fbclk
Tclk_high
Tclk_low
50%DVDD
Figure 4. BITCLK Timing
Tsync_high
Tsync_low
SYNC
VIH
VIL
1/Fsync
Figure 5. SYNC Timing
BITCLK
Tdelay
Tsetup
SDATAIN
SDATAOUT,
SYNC
Trise_clk
BITCLK
Tfall_clk
Thold
Figure 6. Setup and Hold Timing
90%DVDD
10%DVDD
Trise_din
SDATAIN
VIH
VIL
VIH
VIL
VIH
VIL
Tfall_din
90%DVDD
10%DVDD
Trise_sync
SYNC
Tfall_sync
90%DVDD
10%DVDD
Trise_dout
SDATAOUT
Tfall_dout
Figure 7. Signal Rise and Fall Times
(25pF external load; between 10%DVDD and 90%DVDD)
90%DVDD
10%DVDD
MS0502-E-01
- 18 -
2007/04