AK4650 Datasheet, PDF (20/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
OPERATION OVERVIEW
■ Master Clock Source
The AK4650 requires a master clock (MCLK). This master clock is input to the AK4650 by the following three methods:
(1) Connect a X’tal oscillator between XTI and XTO pins.
(2) Input an external CMOS-level clock to the XTI pin.
(3) Input an external clock whose amplitude is greater than 50%DVDD to the XTI pin with AC coupling.
When using a X’tal oscillator, there should be capacitors between XTI/XTO pins and DVSS (Figure 12).
Master Clock
Status
PR5 bit
X’tal Oscillator
(Figure 12)
Oscillator ON
0
(PLL1 pin = “L”)
Oscillator OFF
1
External Clock Direct Input (Figure 13) Clock is input to MCKI pin.
0
(PLL1 pin = “L”)
MCKI pin is fixed to “L”.
1
MCKI pin is fixed to “H”.
1
MCKI pin is Hi-Z
1
External Clock Direct Input (Figure 14) Clock is input to MCKI pin.
0
(PLL1 pin = “H”)
MCKI pin is fixed to “L”.
0
MCKI pin is fixed to “H”.
0
MCKI pin is Hi-Z
0
AC Coupling Input
(Figure 15) Clock is input to MCKI pin.
0
(PLL1 pin = “L”)
Clock isn’t input to MCKI pin.
1
Table 1. Master Clock Status by PR5 bit and MCKPD bit
(1) X’tal Oscillator (PLL1 pin = “L”)
MCKPD bit
0
1
0
0/1
0
1
0
0/1
0
1
0
1
XTI
C
C
XTO
MCKPD = "0"
PR5 = "0"
25kΩ (typ)
PLL1 = "L"
PLL1 = "L"
AK4650
Figure 12. X’tal mode
Note 34. The capacitor values depend on the X’tal oscillator used. (C : typ. 10 ∼ 30pF)
MS0502-E-01
- 20 -
2007/04