AK4650 Datasheet, PDF (67/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of
BITCLK. On the immediately following falling edge of BITCLK, the AK4650 samples the assertion of SYNC. This
falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of
BITCLK, the AK4650 transitions SDATAIN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit
position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AC ’97 controller on the
following falling edge of BITCLK. This sequence ensures that data transitions, and subsequent sample points for both
incoming and outgoing data streams are time aligned.
SY NC
BITCLK
SDATAIN
Codec
Ready
Slot1 Slot2 Slot3
Slot4
Slot5
Slot6
Slot7 Slot8
“1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “0” “0”
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7
Slot 0
Slot11 Slot12
“0” “1/0” “0” “0” “0”
Bit4 Bit3 Bit2 Bit1 Bit0
Slot 1
Figure 51. Slot 0
[Slot 1]: Status Address Port
Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in
slot 2. (Assuming that slot 1 valid bit and slot 2 valid bit in the slot 0 had been tagged “valid” by the AK4650.)
BITCLK
SDATAIN
Slot 0
Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit19
“0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0”
Slot 1
Status Address Port
Slot 2
Figure 52. Slot 1
This address shows register index for which data is being returned in the slot 2. This address port is the copy of slot 1 of
the output frame, and index address input to SDATAOUT is looped back to the AC’97 controller through SDATAIN
even for non-supported register.
For “On Demand” base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4650 will request
new audio data as required by setting the SLOTREQ bits 11 and 10 in slot 1 to 0’s. When no data is required to support the
selected sampling rate, these bits will be 1’s. When SLOTREQ bits are asserted as “send data request” during the current
frame on SDATAIN, AC’97 digital controller should send data onto the corresponding slot in the next frame on
SDATAOUT. If VRA bit is set to “0”, SLOTREQ bits always show “0” and sample rate is tired to 48kHz.
SLOTREQ Bit
19
18-12
11
10
9-0
Description
Reserved (Set to “0”)
Control Register Index (7bit; Set to “0” if tagged invalid)
Slot 3 Request: PCM Lch
“0”: send data request, “1”: do not send
Slot 4 Request: PCM Rch
“0”: send data request, “1”: do not send
Reserved (10bit; Set to “0”)
Table 56. SLOTREQ bit
MS0502-E-01
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2007/04