AK4650 Datasheet, PDF (42/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ Speaker Output
Mono signal [(L+R)/2] converted from stereo DAC output and BEEP input signal can be output via Speaker-amp which
output is BTL. DAC output signal can be input to the Speaker-amp via the ALC2 circuit. This Speaker-amp can output a
maximum of 300mW@ALC2 bit = “0” and 190mW@ALC2 bit = “1”.
ALC2
Po
0
300mW (default)
1
190mW
Table 37. Speaker-Amp Output Power
Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT2, SPP and SPN pins are placed in a Hi-Z state.
When the SPPS bit is “1”, the Speaker-amp is power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and
the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this
mode can reduce pop noise at power-up. When the AK4650 is powered-down, pop noise can be also reduced in
power-save-mode.
PMSPK
0
1
SPPS
x
1
0
Mode
SPP pin
Power-down
Hi-Z
Power-save
Hi-Z
Normal operation
Normal operation
Table 38. Speaker Output Setting
SPN pin
Hi-Z
HVDD/2
Normal operation
(default
)
PMSPK bit
SPPS bit
SPP pin
Hi-Z
Hi-Z
SPN pin _Hi-Z ^HVDD/2
Figure 29. Power-up/Power-down Timing for Speaker-amp
HVDD/2
Hi-Z
■ Mono Output (MOUT2 pin)
The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MO2 bit is “0”, this output is OFF and the
MOUT2 pin is forced to VCOM voltage. The load impedance is 10kΩ (min.). When the PMSPK bit is “0”, the
Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state.
MS0502-E-01
- 42 -
2007/04