AK4650 Datasheet, PDF (69/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ Power On
Note that AK4650 must be in cold reset at power on and RESETN must be “L” until master crystal clock becomes stable,
or cold reset must be done once after master clock is stable.
Vdd
RESETN
SDATA_OUT=”L”
SYNC=”L”
BIT_CLK
Initialize Registers
start up crystal oscillation
Trst2clk
Figure 53. Power On Timing
■ Cold Reset
Note that both SDATAOUT and SYNC must be “L” at the rising edge of RESETN for cold reset.
The AK4650 initializes all registers including the Power-down Control Registers, BIT-CLK is reactivated and each
analog output except for HP-Amp is in Hi-Z state while RESETN pin is “L”.
At the rising edge of RESETN, the AK4650 starts the initialization of ADC and DAC, which takes 1028TS cycles. After
that, the AK4650 is ready for normal operation. At that time, VRA bit is its default value (“0”). Therefore, fs=48kHz and
TS=1/fs=20.83μs.
Status bit in the slot 0 is “0” (not ready) when the AK4650 is in RESET period (“L”) or in initialization process. After
initialization cycles, the status bit goes to “1” (ready).
Trst_low
Trst2clk
RESETN
VIL
SDATA_OUT= “L”
SYNC= “L”
BIT_CLK
Figure 54. Cold Reset Timing
MS0502-E-01
- 69 -
2007/04