AK4650 Datasheet, PDF (29/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.
(1) ALC1 Limiter Operation
When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH bit: Table 15), the
IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits: Table 16) automatically.
When the ZELMN bit = “1”, the timeout period is set by the LTM1-0 bits (Table 17). The operation for attenuation is
done continuously until the IPGA output signal level becomes LMTH or less. If the ALC1 bit does not change into “0”
after completing the attenuation, the attenuation operation repeats while the IPGA output signal level equals or exceeds
LMTH.
When the ZELMN bit = “0”, the timeout period is set by the ZTM1-0 bits (Table 18). This enables the zero-crossing
attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform.
LMTH
0
1
ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 15. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
(default)
LMAT1 LMAT0 ATT STEP
0
0
0.5dB
(default)
0
1
1.0dB
1
0
1.5dB
1
1
2.0dB
Table 16. ALC1 Limiter ATT Step Setting
Note: When IPGA gain is 0dB or less, ALC1 limiter ATT step is fixed to 1 regardless as LMAT1-0 bits.
LTM1 LTM0
ALC1 Limiter Operation Period
8kHz
16kHz
44.1kHz
0
0
0.5/fs
63μs
31μs
11μs
(default)
0
1
1/fs
125μs
63μs
23μs
1
0
2/fs
250μs
125μs
45μs
1
1
4/fs
500μs
250μs
91μs
Table 17. ALC1 Limiter Operation Period at zero crossing disable (ZELMN bit = “1”)
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
128/fs
16ms
8ms
256/fs
32ms
16ms
512/fs
64ms
32ms
1024/fs
128ms
64ms
Table 18. Zero Crossing Timeout Period
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
(default)
MS0502-E-01
- 29 -
2007/04