AK4650 Datasheet, PDF (62/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio
frame where SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is
defined as the “Data Phase”.
Note that SDATAOUT and SDATAIN data is delayed one BITCLK because AC’97 controller causes
SYNC signal high at a rising edge of BITCLK which initiates a frame.
“Output” stream means the direction from AC’97 controller to the AK4650, and “Input” stream means the direction from
the AK4650 to AC’97 controller.
■ AC-Link Protocol
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA
TAG Command Command PCM(dac) PCM(dac) All
All
All
All
All
All
All
All
OUT
Address Data
Left
Right
“0”
“0”
”0”
“0”
“0”
“0”
“0”
“0”
SDATA
TAG
Status Status PCM(adc) All 12bit ADC 12bit ADC All
All
All
All
All 12bit ADC
IN
Address Data
Left
”0”
Data
Data
”0”
“0”
“0”
“0”
“0”
Data
Tag Phase
Data Phase
48kHz
Figure 47. AC-Link protocol
AC-link protocol identifies 13 slots of data per frame. The frequency of SYNC is fixed to 48kHz. Only Slot 0, which is the
Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
MS0502-E-01
- 62 -
2007/04