AK4650 Datasheet, PDF (22/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ System Clock
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 pins (Table 2).
When the external master clock is used, the PLL should be powered-up after the external master clock is input. It takes
0.5ms(typ) for X’tal oscillator to be stable after PR5 bit = “0” which depends on the X’tal. The PLL needs 9ms lock time,
whenever the sampling frequency changes or the PLL is powered-up (VRA bit = “0” → “1”).
When the clock input to MCKI pin stops during normal operation of AC-Link (PR4 = PR5 bits = “0”), the internal PLL
continues to oscillate (a few MHz), and BITCLK output goes to “L” (Table 3).
MCLK and SYNC must be present whenever the ADC or DAC is operating (PR0 = PR1 = PR3 = PR4 = PR5 bits = “0”).
If these clocks are not provided, the AK4650 may draw excess current due to its use of internal dynamically refreshed
logic. If the external clocks are not present, the ADC and DAC must be placed in the power-down mode by setting PR0-6
bits.
PLL1 pin
PLL0 pin
MCKI
L
L
24.576MHz
H
N/A
H
L
3.6864MHz
H
12MHz
Table 2. MCKI Input Frequency
MCKI pin
BITCLK pin
SYNC pin
Power up
Frequency set by PLL1-0
pins (Table 2)
12.288MHz Output
Power down
Refer to Table 1
“L”
Input
Fixed to “L” or “H” externally
Table 3. Clock Operation
PLL Unlock
Frequency set by PLL1-0 pins
(Table 2)
“L”
Input
or
Fixed to “L” or “H” externally
MS0502-E-01
- 22 -
2007/04