AK4650 Datasheet, PDF (43/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
■ ALC2 Operation
Input resistance of the ALC2 (MIN pin) is 24kΩ (typ) and centered around VCOM voltage. Figure 30 shows input-output
relationship at ALC2 operation (0dBV=1Vrms =2.828Vpp).
The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the
Speaker-amp output level exceeds +1.8dBV@HVDD=3.3V. When a continuous signal of +1.8dBV or greater is input to
the ALC2 circuit, the output level is attenuated by ALC2 operation. The change period of the ALC2 limiter operation is
set by the ROTM bit and the attenuation level is 0.5dB/step (Table 39).
When the Speaker-amp output level is equal to or lower than −0.2dBV@HVDD=3.3V, the ALC2 recovery opeation
starts. The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done
until the output level of the Speaker-amp goes to −0.2dBV@HVDD=3.3V. The ALC2 maximum gain is +18dB. The
ROTM bit sets the ALC2 recovery operation period (Table 39).
When the output signal is between +1.8dBV and −0.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit =
“0”, 512/fs = 11.6ms @fs=44.1kHz at the ROTM bit = “1”) starts. This fs value is set by Addr=32H (ADC sampling
frequence). The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization
cycle.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
Operation Start Level
+1.8dBV
−0.2dBV
Period
ROTM bit = “0”
ROTM bit = “1”
2/fs = 45μs@fs=44.1kHz
2/fs = 181μs@fs=11.025kHz
2048/fs = 46.4ms@fs=44.1kHz
512/fs = 46.4ms@fs=11.025kHz
Zero-crossing Detection
Disabled
Enabled (Timeout = 2048/fs)
ATT/GAIN
0.5dB step
1dB step
Table 39. Limiter /Recovery of ALC2 at HVDD=3.3V
SPK Out
+3.8dBV
+1.8dBV
−0.2dBV
(Limitter)
(Recovery)
(ALC2=OFF)
−18.2dBV
DAC In
Figure 30. DAC input – Speaker output relationship (HVDD=3.3V, ALC2 bit = “1”)
MS0502-E-01
- 43 -
2007/04