AK4650 Datasheet, PDF (17/86 Pages) Asahi Kasei Microsystems – 16Bit ΔΣ CODEC with MIC/HP/SPK-AMP & TSC

[AK4650]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, HVDD, DVDD, TSVDD=2.7 ∼ 3.6V; C_L=25pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
PLL1 pin = “L”, PLL0 pin = “L”
Fmclk
-
24.576
-
MHz
PLL1 pin = “H”, PLL0 pin = “L”
Fmclk
-
3.6864
-
MHz
PLL1 pin = “H”, PLL0 pin= “H”
Fmclk
-
12
-
MHz
Duty Cycle
Dmclk
40
-
60
%
AC link Interface Timing
BITCLK frequency
Fbclk
-
12.288
-
MHz
BITCLK clock Period (Tbclk=1/Fbclk)
Tbclk
-
81.38
-
ns
BIT_BLK low pulse width
Tclk_low
36
40.7
45
ns
BIT_BLK low pulse width
Tclk_high
36
40.7
45
ns
BITCLK rise time
Trise_clk
-
-
6
ns
BITCLK fall time
Tfall_clk
-
-
6
ns
SYNC frequency
Fsync
-
48
-
kHz
SYNC low pulse width
Tsync_low
-
19.5
-
(240 cycle)
μs
(Tbclk)
SYNC high pulse width
Tsync_high
-
1.3
-
μs
(16 cycle)
(Tbclk)
SYNC rise time
Trise_sync
-
-
6
ns
SYNC fall time
Tfall_sync
-
-
6
ns
Setup time (SYNC, SDATAOUT)
Tsetup
14
-
-
ns
Hold time (SYNC, SDATAOUT)
Thold
25
-
-
ns
SDATAIN delay time from BITCLK rising Tdelay
-
-
15
ns
edge
SDATAIN rise time
Trise_din
-
-
6
ns
SDATAIN fall time
Tfall_din
-
-
6
ns
SDATAOUT rise time
Trise_dout
-
-
6
ns
SDATAOUT fall time
Tfall_dout
-
-
6
ns
Cold Reset (SDATAOUT = “L”, SYNC = “L”)
RESETN active low pulse width
Trst_low
1.0
-
-
μs
RESETN inactive to BITCLK delay
PLL1 pin = “L” (External clock)
Trst2clk
-
42
-
μs
PLL1 pin = “L” (X’tal oscillator)
Trst2clk
-
0.5
-
ms
PLL1 pin = “H”, PLL0 pin = “L”
Trst2clk
-
9.5
-
ms
PLL1 pin = “H”, PLL0 pin = “H”
Trst2clk
-
3.2
-
ms
Warm Reset Timing
SYNC active high pulse width
Tsync_high
1.0
1.3
-
μs
(16 cycle)
(Tbclk)
SYNC inactive to BITCLK delay
PLL1 pin = “L” (External clock)
Trst2clk
-
42
-
μs
PLL1 pin = “L” (X’tal oscillator)
Tsync2clk
-
0.5
-
ms
PLL1 pin = “H”, PLL0 pin = “L”
Tsync2clk
-
9.5
-
ms
PLL1 pin = “H”, PLL0 pin = “H”
Tsync2clk
-
3.2
-
ms
AC-link Low Power Mode Timing
End of Slot 2 to BITCLK, SDATAIN Low Ts2_pdwn
-
-
1.0
μs
Activate Test Mode Timing
Setup to trailing edge of RESETN
Tsetup2rst
15.0
-
-
ns
Hold from RESETN rising edge
Thold2rst
100
-
-
ns
Rising edge of RESETN to Hi-Z
Toff
-
-
50
ns
Falling edge of RESETN to “L”
Tlow
-
-
50
ns
MS0502-E-01
- 17 -
2007/04