AK4538 Datasheet, PDF (68/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
MCKO bit
(Addr:03H, D4)
PMPLL bit
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
External MCLK
(1)
(2)
(3)
Input
Example :
Audio I/F : I²S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:04H, Data:62H
(2) Addr:01H, Data:80H
(3) Stop external clock
Figure 58. Stop of Clock Sequence(3)
<Example>
(1) Stop MCKO output : MCKO bit = “1” → “0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
n Power down
Power down VCOM(PMVCM= “1” → “0”) after all blocks except VCOM are powered down and MCLK stops. The
AK4538 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0198-E-01
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