AK4538 Datasheet, PDF (53/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
Addr
09H
Register Name
ALC Mode Control 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
0
0
LMTH:ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 30)
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.
Default is “0”.
LMTH
0
1
ALC1 Limiter Detection Level
ALC1 Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 30. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC1 Recovery GAIN Step (see Table 31)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the ALC1 recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
RATT
GAIN STEP
0
1
Default
1
2
Table 31. ALC1 Recovery Gain Step Setting
LMAT1-0: ALC1 Limiter ATT Step (see Table 32)
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH,
the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is
47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts, resulting
in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = “00”
(−8dB), it clips to “00”.
LMAT1 LMAT0 ATT STEP
0
0
1
Default
0
1
2
1
0
3
1
1
4
Table 32. ALC1 Limiter ATT Step Setting
ZELM: Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and the
IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery
operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
ALC1: ALC1 Enable Flag
0: ALC1 Disable (Default)
1: ALC1 Enable
ALC2: ALC2 Enable Flag
0: ALC2 Disable
1: ALC2 Enable (Default)
MS0198-E-01
- 53 -
2003/5