AK4538 Datasheet, PDF (62/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
3. When an external clock is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
External MCLK
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
BICK, LRCK
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
(1)
(2)
(3)
Input
40ms(max)
E xam p le :
Audio I/F Format : I²S
BICK frequency at Master Mode : 64fs
Inp u t M a s t e r C lo c k S e lect at P L L M o d e : 1 1 . 2 8 9 6 M H z
O utput M aster C lo c k F r e q u e n c y : 6 4 f s
(1) Addr:0 1 H , Data:00H
(2) Input external MCLK
(3) Addr:0 1 H , Data 2 0 H
(4)
(5)
Output
(4) Addr:0 4 H , Data 4AH
(5) MCKO output starts
(6)
Input
(6) BICK and LRCK input start
(7)
00
XX
(7) Addr:0 4 H , Data 6AH
Figure 50. Clock Set Up Sequence(3)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
MS0198-E-01
- 62 -
2003/5