AK4538 Datasheet, PDF (11/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH 70%DVDD
-
Low-Level Input Voltage
VIL
-
-
Input Voltage at AC Coupling
(Note 25)
VAC 50%DVDD
-
High-Level Output Voltage
(Iout=−200µA)
VOH DVDD−0.2
-
Low-Level Output Voltage
(Except SDA pin: Iout=200µA)
VOL
-
-
(
SDA pin: Iout= 3mA)
VOL
-
-
Input Leakage Current
Iin
-
-
Note 25. When AC coupled capacitor is connected to MCKI pin.
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator Frequency
11.2896
-
External Clock Frequency
fCLK
1.792
-
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
AC Pulse Width (Note 26) tACW 0.4/fCLK
MCKO Output Frequency
fMCK
0.224
Duty Cycle : except fs=32kHz dMCK
40
50
fs=32kHz at 256fs (Note 27) dMCK
33
LRCK Frequency
Frequency
Duty Cycle
Slave mode
Master mode
fs
7
Duty
45
Duty
50
Audio Interface Timing
Slave mode
BICK Period
tBCK
312.5
BICK Pulse Width Low
tBCKL
130
Pulse Width High
tBCKH
130
LRCK Edge to BICK “↑” (Note 28)
tLRB
50
BICK “↑” to LRCK Edge
(Note 28)
tBLR
50
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Master mode
BICK Frequency
fBCK
64fs
BICK Duty
dBCK
50
BICK “↓” to LRCK
tMBLR
−80
BICK “↓” to SDTO
tBSD
−80
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Max
-
30%DVDD
-
-
Units
V
V
V
V
0.2
V
0.4
V
±10
µA
max
12.288
12.288
12.288
60
48
55
Units
MHz
MHz
ns
ns
ns
MHz
%
%
kHz
%
%
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
Hz
%
80
ns
80
ns
ns
ns
Note 26. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 4)
Note 27. PMPLL bit = “1”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
MS0198-E-01
- 11 -
2003/5