AK4538 Datasheet, PDF (43/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
n Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMVCM
R/W
0
D6
PMBPS
R/W
0
D5
PMBPM
R/W
0
D4
PMLO
R/W
0
D3
PMMO
R/W
0
D2
PMAUX
R/W
0
D1
PMMIC
R/W
0
D0
PMADC
R/W
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms@44.1kHz) starts. After
initializing, digital data of the ADC is output.
PMMIC: MIC In Block Power Control
0: Power down (Default)
1: Power up
PMAUX: AUX In Power Control
0: Power down (Default)
1: Power up
PMMO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMLO: Line Out Power Control
0: Power down (Default)
1: Power up
PMBPM: Mono BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register
values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=PMSPK= “0” or PDN pin =
“L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.
MS0198-E-01
- 43 -
2003/5