AK4538 Datasheet, PDF (55/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
Addr
0BH
Register Name
Input PGA Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
IPGA6-0: Input Analog PGA (see Table 34)
Default: “10H” (0dB)
When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. IPGA
gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC is
changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
When IPGA6-0 bits are read, the register values written by the last write operation are read out regardless the
actual gain.
DATA (HEX) GAIN (dB)
STEP
47
+27.5
46
+27.0
45
+26.5
:
:
36
+19.0
:
:
10
+0.0
:
:
0.5dB
06
−5.0
05
−5.5
04
−6.0
03
−6.5
02
−7.0
01
−7.5
00
−8.0
Table 34. Input Gain Setting
Default
Addr
0CH
0DH
Register Name
Lch Digital ATT Control
Rch Digital ATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL/R7-0: Digital ATT Output Control (see Table 21)
Default: “00H” (0dB)
MS0198-E-01
- 55 -
2003/5