AK4538 Datasheet, PDF (36/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
n ALC2 Operation
Input resistance of the ALC2 is 24kΩ (typ) and centered around VCOM voltage, and the input signal level is –3.1dBV. (see
Figure 31. 0dBV=1Vrms=2.828Vpp)
The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the input signal
exceeds –5.2dBV (=FS-1.9dB@HVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to the ALC2
circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery
operation period.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit = “0”,
512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = “1”) starts. The ALC2 is disabled during the initilization cycle and the
ALC2 starts after completing the initilization cycle.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
Operation Start Level
−5.2dBV
−7.2dBV
Period
ROTM bit = “0”
ROTM bit = “1”
2/fs = 45µs (at 44.1kHz)
2048/fs=46.4ms (at 44.1kHz)
2/fs = 180µs (at 11.025kHz) 512/fs=46.4ms (at 11.025kHz)
Zero-crossing Detection
No
Yes (Timeout = Period Time)
ATT/GAIN
0.5dB step
1dB step
Table 24. Limiter /Recovery of ALC2 at HVDD=3.3V
FS
FS-12dB
-3.3dBV
-8dB
-15.3dBV
-8dB
FS-1.9dB = -5.2dBV
-3.3dBV _-1.9dB
+5.6dB
0.4dBV
-1.6dBV
Full-differential
0dBV
+4.1dB
-11.3dBV
-15.3dBV
-23.3dBV
+8.1dB
+16.1dB
-5.6dBV
Single-ended
-0.4dB
-10dBV
FS-3.9dB = -7.2dBV
-20dBV
-30dBV
ATT+DAC
ALC2
SPK-AMP
Figure 31. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=−8.0dB)
MS0198-E-01
- 36 -
2003/5