AK4538 Datasheet, PDF (61/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
2. When X'tal is used in PLL mode. (Master mode)
MCKPD bit
(Addr:01H, D7)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
PS1-0 bits
(Addr:04H, D5-4)
MCKO pin
(1)
20ms(typ) ⁽²⁾
40msec(max)
(3)
00
XX
(4)
Output
E xam p le :
A u d io I/F F o r m a t : I²S
BICK frequency at M a ster Mode : 64fs
Inp u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s t e r C lo c k F re q ue n c y : 6 4 f s
(1 ) Addr:01H, Data:40H
(2 ) Addr:01H, Data:60H
(3 ) Addr:04H, Data 6AH
(4 ) MCKO, BICK and LRCK output starts
BICK, LRCK
(Master Mode)
Output
Figure 49. Clock Set Up Sequence(2)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and and power-up the X’tal oscillator: PMXTL
bit = “0” → “1”
(2) Power-up PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at the
same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”. This
time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(4) MCKO, BICK and LRCK are output after PLL lock time.
MS0198-E-01
- 61 -
2003/5