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AK4538 Datasheet, PDF (12/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP | |||
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ASAHI KASEI
[AK4538]
Parameter
Symbol
min
Control Interface Timing (4-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN âHâ Time
CSN âââ to CCLK âââ
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
50
CCLK âââ to CSN âââ
tCSH
50
CDTO Delay
tDCD
CSN âââ to CDTO Hi-Z
tCCZ
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse) tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 29) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Reset Timing
PDN Pulse Width
PMADC âââ to SDTO valid
(Note 30)
(Note 31)
tPD
150
tPDV
Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 30. The AK4538 can be reset by the PDN pin = âLâ.
Note 31. This is the count of LRCK âââ from the PMADC bit = â1â.
typ
2081
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
70
ns
100
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
ns
1/fs
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C
patent to use the components in the I2C system, provided the system conform to the I2C specifications
defined by Philips.
MS0198-E-01
- 12 -
2003/5
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