AK4538 Datasheet, PDF (20/70 Pages) Asahi Kasei Microsystems – 16Bit DS CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4538]
n System Clock
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table 2 and Table 3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table 4
and the MCKO output enable is controlled by the MCKO bit. If PS1-0 bits are changed before LRCK is input,
MCKO is not output. PS1-0 bits should be changed after LRCK is input in slave mode.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted. If X'tal and
PLL are powered-up at the same time or PLL is powered-up before external master clock is inputted,
the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”. The PLL needs 40ms
lock time, whenever the sampling frequency changes or the PLL is powered-up (PMPLL bit= “0” → “1”).
If the sampling frequency is changed and the PLL goes to unlock state when the DAC is operated(PMDAC bit= “1”), the
DAC data should be soft-muted or “0”. In case of the ADC(PMADC bit = “1”), the ADC data acquired during the
frequency change may be erroneous and therefore should not be used.
LRCK and BICK are output from the AK4538 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to “L”
(see Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present whenever
the AK4538 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4538 may draw
excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the
AK4538 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
0
1
2
3
PLL1
PLL0
MCKI
0
0
12.288MHz
0
1
11.2896MHz
1
0
12MHz
1
1
N/A
Table 2. MCKI Input Frequency (PLL Mode)
Default
FS2
FS1
FS0
Sampling Frequency
0
0
0
44.1kHz
Default
0
0
1
22.05kHz
0
1
0
11.025kHz
0
1
1
48kHz
1
0
0
32kHz
1
0
1
24kHz
1
1
0
16kHz
1
1
1
8kHz
Table 3. Sampling Frequency (PLL Mode)
Mode
PS1
PS0
MCKO
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
MS0198-E-01
- 20 -
2003/5