AK7740ET Datasheet, PDF (5/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
(2) Pin function
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin name
AINL3
AINR2
AINL2
AINR1
AINL1
VREFH
AVDD
AVSS
DVSS
DVDD
XTI
XTO
CLKO
JX
SMODE
LRCLK
BITCLK
SDIN
SDINA
I/O
Function
I ADC single-ended analog Lch input pin 3
I ADC single-ended analog Rch input pin 2
I ADC single-ended analog Lch input pin 2
I ADC single-ended analog Rch input pin 1
I ADC single-ended analog Lch input pin 1
I Analog reference voltage input
Connect to AVDD (pin 7), and bypass with 0.1uF and
10uF capacitors between this pin and AVSS.
- Analog power supply 3.3V typical
- Analog ground
- Digital ground
- Digital power supply 3.3V typical
Master clock input
I Connect a crystal oscillator between this pin and the XTO pin,
or input an external CMOS clock signal to the XTI pin.
Crystal oscillator output
O When a crystal oscillator is used, connect between XTI and XTO.
When an external clock is used, keep this pin open
Clock output
O Outputs the XTI clock.
Allows the output to be set to "L" by control register setting.
I External condition jump (pulldown)
Slave/master mode selector
I Sets LRCLK and BITCLK to input or output mode.
SMODE="L": Slave mode (clock input mode)
SMODE="H": Master mode (clock output mode)
LR channel select clock
I/O SMODE="L": Slave mode: Inputs the fs clock
SMODE="H": Master mode: Outputs the fs clock
Serial bit clock
I/O SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks
SMODE="H": Master mode: Outputs 64 fs clocks
DSP serial data input ( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
DSP serial data input (Pulldown)
I When using the ADC, leave open or connect to DVSS.
Compatible with MSB justified 24 bits.
Classification
Analog section
Analog
Power Supply
Digital
Power Supply
System clock
System clock
Condition input
Control
System clock
Digital section
Serial input data
<Pre-E-01>
-5-
2006/10