AK7740ET Datasheet, PDF (27/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
(6) Audio data interface (internal connection mode)
The serial audio data pins SDIN, SDINA, SDOUT and SDOUTA are interfaced with an external system, using
LRCLK and BITCLK. The control registers
data format is MSB-first two's complement.
(CONT2 and CONT3)
The data format can be
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control register CONT0:DIF (D5) to “1” (all input/output audio data pin interfaces are in I²S compatible mode.)
The input SDIN and SDINA formats are MSB justified 24-bit at initialization. Setting the control registers CONT0:
DIF1 (D4), DIF0 (D3) will cause SDIN to be compatible with LSB justified 24-bit, 20-bit and 16-bit. (SDINA is fixed
to 24-bit MSB justified only) (Note: CONT0 DIF(D5)=0). Individual setting of SDIN and SDINA is not allowed.
The output SDOUT is fixed at 24-bit MSB justified only.
In slave mode, BITCLK corresponds to both 64fs and 48fs. 64fs is the recommended BITCLK. 64fs examples are
illustrated here:
6-1) Standard input format (DIF = 0: default set value)
a) Mode 1 (DIF1, DIF0 = 0,0: default set value)
LRCLK
BITCLK
SDIN,SDINA
31 30 29
M 22 21
Left ch
10 9 8 7 6 5 4 3 2 1 0 31 30 29
21L
M 22 21
Right ch
10 9 8 7 6 5 4 3 2 1 0
21L
M : MSB, L : LSB
* For MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB.
b) Mode 2, Mode 3, Mode 4
LRCLK
Left ch
Right ch
BITCLK
SDIN
mode2
SDIN
mode3
SDIN
mode4
SDIN
SDIN
SDIN
31 30
23 22 21 20 19 18 17 16 15 1 0 31 30
23 22 21 20 19 18 17 16 15
Don't Care M 22 21 20 19 18 17 16 15 1 L Don't Care M 22 21 20 19 18 17 16 15
Don't Care
M 18 17 16 15 1 L Don't Care
M 18 17 16 15
Don't Care
M 1 L Don't Care
M
M : MSB, L : LSB
Mode 2: (DIF1, DIF0) = (0, 1) LSB justified 24-bit
Mode 3: (DIF1, DIF0) = (1, 0) LSB justified 20-bit
Mode 4: (DIF1, DIF0) = (1, 1) LSB justified 16-bit
10
1L
1L
1L
<Pre-E-01>
- 27 -
2006/10