AK7740ET Datasheet, PDF (30/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
7-1) Write during reset phase
7-1-a) Control register write (during reset phase)
The data is comprised of two bytes that perform control register write operations (during reset phase). When the
current data has been entered, the new data is sent when the 16^th cycle of SCLK.
Data transfer procedure
c Command code 60h,64h,68h,6Ch
d Control data
(D7 D6 D5 D4 D3 D2 D1 D0)
For the function of each bit, see the description of control registers, (section 2).
S_RESET
RQ
SCLK
SI
SO
60h
D7 ***D1 D0
64h
D7 ***D1 D0
Note) It must be set always 0 to D0
Control registers write operation
<Pre-E-01>
- 30 -
2006/10