AK7740ET Datasheet, PDF (25/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
(4) Resetting
The AK7740 has two reset pins: INIT_RESET and S_RESET .
The INIT_RESET pin sets up VREF and initializes the AK7740, as shown in "Power supply startup sequence
section 3)."
The system is reset when S_RESET =”L”. (Description of "reset" is for "system reset".)
Under of system reset, program write operation executes normally (except for write operation during running).
The ADC and DAC sections are also reset during system reset. (The ADC output is MSB first 00000h and the DAC
output is AVDD/2). However, VREF will be active and LRCLK and BITCLK in the master mode will be inactive.
Release system reset by setting S_RESET to "H", which will activate the internal counter. This counter generates
LRCLK and BITCLK in the master mode. When the system reset is released in slave mode, internal timing will be
actuated in synchronization with "Ç" of LRCLK (when the standard input format is used). Timing between the
external and internal clocks is adjusted at this time. If the phase difference between LRCLK and internal timing is
within ±1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with the internal
timing remaining unchanged. If the phase difference exceeds this range, the phase is adjusted by synchronization with
"Ç" of LRCLK (when the standard input format is used). This circuit prevents failure of synchronization with the
external circuit. For some time after returning to the normal state after loss of synchronization, normal data will not
be valid. Change the frequency of the clock, SMODE or analog input selector while the system is in reset.
When S_RESET is set to “H”, the reset state is cancelled, and the internal DRAM is cleared from the rising edge of
LRCLK. It takes 8fs (167usec at fs = 48kHz) to clear the internal DRAM.
The ADC section can output 516 cycles LRCLK after its internal counter starts. (The internal counter starts at the first
rising edge of LRCLK in master mode. In slave mode, it starts at the end of 2-LRCLK after release of system reset.)
The AK7740 is in normal operation mode when S_RESET is set to "H".
When INIT_RESET or S_RESET changes, the status of the DAC section also changes to power down or release
mode, which causes a click noise at the output. The SMUTE function does not mute this click, ao an external mute
circuit is required to avoid any click noise.
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2006/10