AK7740ET Datasheet, PDF (35/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
7-2) Read during reset phase
7-2-a) Control register data read (during reset phase)
To read data written into the control registers, input the command code and 16 bits of SCLK. After the command code
input, the data D7 to D1 outputs from SO synchronized with the falling edge of SCLK. D0 is invalid, so ignore this
bit.
Data transfer procedure
c Command code 70h,74h,78h,7Ch
S_RESET
RQ
SCLK
SI
SO
70h (example)
D7 **** D1
74h (example)
D7 **** D1
Reading of Control Register data
<Pre-E-01>
- 35 -
2006/10