AK7740ET Datasheet, PDF (29/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
(7) Interface with microcontroller
The microcontroller interface consists of six control signals; RQ (request), SCLK (serial data input clock), SI
(serial data input), SO (serial data output), RDY (ready) and DRDY (data ready). Both write and read operations are
enabled during system reset and run modes. During reset , writing to the control register, program RAM, coefficient
RAM, offset RAM, external conditional jump code, and reading from the program RAM, coefficient RAM and offset
RAM, are enabled. During the run phase, writing of coefficient RAM, offset RAM and external conditional jump
code, and reading of data on the DBUS (data bus) from the SO, are enabled. The data is MSB first serial I/O.
To transfer data to the microcontroller, start by setting RQ “L”, which enables a data read from the DBUS. The
AK7740 reads SI data when SCLK rises, and outputs to SO when SCLK falls. The data format is command followed
by address.
When RQ changes to “H”, then one command is finished. New command requests require setting RQ to “L”
again. When the DBUS data is read, leave RQ =”H” (command code input is not required).
Conditions
for use
RESET
phase
RUN
phase
Code name
CONT0
CONT1
CONT2
CONT3
PRAM
CRAM
OFRAM
External condition jump
Test
CRAM rewrite
preparation
CRAM rewrite
OFRAM rewrite
preparation
OFRAM rewrite
External condition jump
Command Code List
Command code Note:
WRITE READ
60h
70h For the function of each bit,
64h
74h See the description of Control
68h
78h Registers
6Ch
7Ch
C0h
C1h
A0h
A1h
90h
91h
C4h
-
82h
-
Reserved for test
A8h
-
Must occur before CRAM rewrite
A4h
-
98h
-
Must occur before OFRAM rewite
94h
-
C4h
-
Same command as RESET
NOTE: Do not send any other command codes.
If there is no communication with the microcontroller, set the SCLK to "H” and the SI to "L" for use.
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2006/10