AK7740ET Datasheet, PDF (32/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
7-1-c) Coefficient RAM write (during reset phase)
The data comprising a set of five bytes is used to perform coefficient RAM write operations (during reset phase).
When all data has been transferred, the RDY terminal goes "H". Upon completion the CRAM write, RDY goes to
"H" to allow the next data to be inputted. When writing data of continuous addresses, input the data as they are (no
command code or address is required). To write discontinuous data, shift the RQ terminal from "H" to "L". Then
input the command code, address and data in that order.
Data transfer procedure
c Command code A0h ( 1 0 1 0 0 0 0 0 )
d Address upper
( 0 0 0 0 0 0 0 A8)
e Address lower
(A7 . . . . . . . A0)
f Data
(D15 . . . . . . D8)
g Data
(D7 . . . . . . D0)
S_RESET
RQ
SCLK
SI
RDY
SO
10100000 0000000 A8 A7****A1A0 D15****D0 D15****D0
Input of continuous address data into CRAM
S_RESET
RQ
SCLK
SI
RDY
SO
10100000 0000000 A8 A7***A1A0 D15****D0
10100000 0000000 A8 A7***A1A0 ^D15*
Input of discontinuous address data into CRAM
<Pre-E-01>
- 32 -
2006/10