AK7740ET Datasheet, PDF (37/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
7-2-c) CRAM data read (during reset phase)
To read out the coefficient data, input the command code and the address to be read out. After that, set SI to "H" and
SCLK to "L”. The data is clocked out from SO synchronized with the falling edge of SCLK.If there are continuous
addresses to be read, repeat the above procedure starting from the step where SI is set to "H".
Data transfer procedure
c Command code A1h
d Address upper
e Address lower
(1 0 1 0 0 0 0 1)
( 0 . . . . . . A8)
(A7 . . . . . . A0)
S_RESET
RQ
SCLK
SI
SO
RDY
10100001 0000000A8 A7 **** A1A0
D15 **** D0
D15 **** D0
Reading of CRAM data
<Pre-E-01>
- 37 -
2006/10