AK7740ET Datasheet, PDF (11/48 Pages) Asahi Kasei Microsystems – 24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7740ET]
(5) Switching characteristics
5-1) System clock
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
Min
Master clock (XTI)
a) With crystal oscillator
384fs: frequency
fMCLK
12.288
512fs: frequency
fMCLK
16.384
b) With external clock:
Duty factor (≤18.432MHz)
40
(>18.432MHz)
45
:Frequency
fMCLK
10.0
: High level width
tMCLKH
16
: Low level width
tMCLKL
16
Clock rise time
tCR
Clock fall time
tCF
LRCLK sampling frequency
fs
32
Slave mode :clock rise time
tLR
Slave mode :clock fall time
tLF
BITCLK
Note 1) fBCLK
48
Slave mode: High level width
tBCLKH
150
Slave mode: Low level width
tBCLKL
150
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
Note 1) 48fs mode can only be applied in slave mode.
5-2) Reset
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
min
INIT_RESET
Note 1) ^tRST
150
S_RESET
tRST
150
Typ
18.432
24.576
50
50
24.576
48
1
64
typ
Max
Unit
19
MHz
25
MHz
60
%
55
25
MHz
ns
ns
6
ns
6
ns
50
kHz
fs
6
ns
6
ns
fs
ns
ns
6
ns
6
ns
max
Unit
ns
ns
Note 1) “L” is acceptable when power is turned on, but ”H” requires a stable master clock input.
<Pre-E-01>
- 11 -
2006/10