AK4665A Datasheet, PDF (38/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
4) DAC → Line Out
Power Supply
PDN pin
DACL,
DACR bits
PMVCM bit
Clock Input
(1) >150ns
(2)
>0
(4)
Don’t care
Don’t care
PMDAC bit
DAC Internal
State
SDTI pin
PMLO bit
ATTL/R7-0 bit
(3) >0
PD(Power-down)
00H(MUTE)
Normal Operation
PD
FFH(0dB)
00H(MUTE)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
10H
(6) GD (7) 1061/fs (6) (7)
(Hi-Z)
(5)
LOUT/ROUT pins
(5)
(Hi-Z)
Figure 24. Power-up/down Sequence of DAC and Line Out
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) DACL and DACR bits should be changed to “1” after PDN pin goes to “H”. Each path is switched-on during the
transition time set by FS3-0 and PTS1-0 bits.
(3) PMDAC and PMLO bits should be changed to “1” after DACL and DACR pins are changed to “1”.
(4) External clocks (MCLK, BICK and LRCK) are needed to operate DAC. External clocks are also needed for each
path (DACL, LINL, MINL, DACR, RINR and MINR bits) setting.
(5) When PMLO bit is changed to “1”, pop noise is output from LOUT/ROUT pins.
(6) Digital output corresponding to analog input has the group delay (GD) of 17.5/fs (=397µs@fs=44.1kHz).
(7) The transition time for digital volume is set by ATS bit. The initial value is 1061/fs (=24ms@fs=44.1kHz).
MS0440-E-01
- 38 -
2006/05