AK4665A Datasheet, PDF (10/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.6 ∼ 3.6V; TVDD=1.6∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
2.048
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
LRCK Timing
Frequency
fs
8
Duty Cycle
Duty
45
Serial Interface Timing (Note 18)
BICK Period
tBCK
325.5
BICK Pulse Width Low
tBCKL
130
Pulse Width High
tBCKH
130
LRCK Edge to BICK “↑” (Note 19)
tLRB
50
BICK “↑” to LRCK Edge (Note 19)
tBLR
50
LRCK to SDTO(MSB)
tLRS
-
BICK “↓” to SDTO
tBSD
-
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Power-down & Reset Timing
PDN Pulse Width (Note 20)
tPD
150
PMADC “↑” to SDTO valid (Note 21)
tPDV
-
Note 18. Refer to “Serial Data Interface”.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. The AK4665A can be reset by bringing PDN= “L” to “H” only upon power up.
Note 21. This is the count of LRCK “↑” from PMADC bit=”1”.
typ
-
-
-
44.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2081
max Units
24.576
-
-
MHz
ns
ns
48
kHz
55
%
-
ns
-
ns
-
ns
-
ns
-
ns
80
ns
80
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
1/fs
MS0440-E-01
- 10 -
2006/05