AK4665A Datasheet, PDF (13/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4665A are MCLK (256fs/512fs), LRCK (fs) and BICK. The master clock
(MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The
sampling frequency is selected by FS3-0 bits (refer to Table 1). The frequency of MCLK is detected automatically, and
the internal master clock becomes the appropriate frequency. Table 2 shows system clock example.
FS3
FS2
FS1
FS0
fs
0
0
0
0
44.1kHz Default
0
0
0
1
32kHz
0
0
1
0
48kHz
1
0
0
0
22.05kHz
1
0
0
1
16kHz
1
0
1
0
24kHz
1
1
0
0
11.025kHz
1
1
0
1
8kHz
1
1
1
0
12kHz
Others
N/A
Table 1. Sampling Frequency
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
MCLK (MHz)
256fs
512fs
2.048
4.096
2.8224
5.6448
3.072
6.144
4.096
8.192
5.6448
11.2896
6.144
12.288
8.192
16.384
11.2896
22.5792
12.288
24.576
Table 2. Systems Clock Example
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
External clocks (MCLK, BICK and LRCK) are needed to operate ADC, DAC, ALC2 or HP-Amp. External clocks are
also needed for each path setting of HP-Amp (DACHL, LINHL, MINHL, DACHR, RINHR, MINHR and HPMTN bits)
and Lineout (DACL, LINL, MINL, DACR, RINR and MINR bits) when MOFF8 bit = “0” or MOFF9 bit = “0”. All
external clocks (MCLK, BICK and LRCK) should always be present whenever ADC, DAC, ALC2 or HP-Amp is in
normal operation mode (PMADC bit = “1”, PMDAC bit = “1”, PMLO=ALC2 bits = “1” or PMCP=PMHPL=PMHPR
bits = “1”). If these clocks are not provided, the AK4665A may draw excess current and will not operate properly because
it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4665A
should be placed in power-down mode (PDN pin = “L” or PMADC=PMDAC=ALC2=PMCP=PMHPL=PMHPR bits =
“0”).
MS0440-E-01
- 13 -
2006/05