AK4665A Datasheet, PDF (34/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
„ Charge Pump Circuit
The internal charge pump circuit generates negative voltage from HVDD voltage. The generated voltage is used to
headphone amplifier. When PMCP bit is set to “1”, the charge pump circuit is powered-up. All clocks (MCLK, BICK and
LRCK) should be supplied at this time. The power-up time of charge pump circuit depends on FS3-0 bits (Table 40).
FS3
0
0
0
1
1
1
1
1
1
„ System Reset
Power up time of
FS2
FS1
FS0
fs
Charge Pump
Circuit
0
0
0
44.1kHz
512/fs = 11.6ms
0
0
1
32kHz
256/fs = 8.0ms
0
1
0
48kHz
512/fs = 10.7ms
0
0
0
22.05kHz
256/fs = 11.6ms
0
0
1
16kHz
128/fs = 8.0ms
0
1
0
24kHz
256/fs = 10.7ms
1
0
0
11.025kHz 128/fs = 11.6ms
1
0
1
8kHz
64/fs = 8.0ms
1
1
0
12kHz
128/fs = 10.7ms
Others
N/A
N/A
Table 40. Power up time of Charge Pump Circuit
Default
The AK4665A should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, all blocks (VCOM,
ADC, DAC, HPL, HPR, Lineout and charge pump circuit) switch to the power-down state. The contents of the control
register are maintained until the reset is done.
ADC exits reset and power down state after PMADC bit is changed to “1”, and then ADC is powered-up and the internal
timing starts clocking by LRCK edge. ADC is in power-down mode until MCLK and LRCK are input. DAC also exits
reset and power down state when MCLK and LRCK are input after PMDAC bit is changed to “1”.
MS0440-E-01
- 34 -
2006/05