AK4665A Datasheet, PDF (35/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
„ Power-Up/Down Sequence
1) ADC (MICIN)
Power Supply
PDN pin
FS3-0, DFS bits
PMVCM bit
Clock Input
PMADC bit
ADC Internal
State
MICIN pin
SDTO pin
(1) >150ns
0H, 0
(2) >0
(3) >0
XH, X
0H, 0
(5)
Don’t care
Don’t care
(4) >0
(7) 2081/fs
PD(Power-down)Init Cycle
Normal Operation
PD
(6)
(Hi-Z)
(8) GD
(Hi-Z)
(8) GD
Figure 21. Power-up/down Sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0 and DFS bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set.
(4) PMADC bit should be changed to “1” after PMVCM bit is changed to “1”.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate ADC.
(6) When PMADC bit is changed to “1”, MICIN pin is biased to VCOM voltage. Rising time constant is determined by
input capacitor for AC coupling and input resistance. In case of 0.22µF input capacitor, time constant is
τ = 0.22µF x 30kΩ = 6.6ms (typ) at MGAIN1 bit = “1”
τ = 0.22µF x 60kΩ = 13.2ms (typ) at MGAIN1 bit = “0”
(7) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state.
SDTO is “L” at that time.
(8) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µs@fs=44.1kHz).
MS0440-E-01
- 35 -
2006/05