AK4665A Datasheet, PDF (21/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
3. Example for ALC1 Operation
Table 15 shows the examples of the ALC1 setting.
Register Name
LMTH
ZELMN
ZTM1-0
WTM1-0
REF7-0
IVOL7-0
LMAT1-0
RGAIN1-0
ALC1
Comment
Data
8kHz
16kHz
32kHz
Limiter detection Level
00
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
00
8ms
Recovery waiting period
*WTM1-0 bits should be the same data 00
8ms
as ZTM1-0 bits
Maximum gain at recovery operation E1H
+30dB
Gain of IVOL
91H
0dB
Limiter ATT step
00
0.375dB
Recovery GAIN step
00
0.375dB
ALC1 enable
1
Enable
Table 15. Example for the ALC1 setting
fs
11.025kHz
22.05kHz
44.1kHz
−4.1dBFS
Enable
8.7ms
8.7ms
+30dB
0dB
0.375dB
0.375dB
Enable
12kHz
24kHz
48kHz
−4.1dBFS
Enable
8ms
8ms
+30dB
0dB
0.375dB
0.375dB
Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed after the ALC1
operation is finished by ALC1 bit = “0” or PMADC bit = “0”.
- LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 8ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC1 bit = “1”
WR (IVOL7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(1) Addr=05H, Data=91H
(2) Addr=02H, Data=00H
WR (REF7-0)
(3) Addr=04H, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC1= “1”)
(4) Addr=03H, Data=20H
ALC1 Operation
Note : WR : Write
Figure 13. Registers set-up sequence at ALC1 operation
MS0440-E-01
- 21 -
2006/05