AK4665A Datasheet, PDF (30/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
(3) Example for ALC2 Operation
Table 29 shows the examples of the ALC2 setting. The ALC2 operation starts from 0dB.
Register Name
LMTHP
LTMP1-0
WTMP1-0
REFP7-0
LMATP1-0
RGAINP
PTS1-0
ALC2
Comment
Data
8kHz
16kHz
32kHz
Limiter detection Level
1
−11.5dBV
Maximum gain at recovery operation
10
500µs
Recovery waiting period
11
512ms
Maximum gain at recovery operation
30H
+12dB
Limiter ATT Step
00
0.5dB
Recovery GAIN Step
0
0.5dB
ALC2 recovery transition time
11
128ms
ALC2 Enable bit
1
Enable
Table 29. Example for the ALC2 setting
fs
11.025kHz
22.05kHz
44.1kHz
−11.5dBV
544µs
557ms
+12dB
0.5dB
0.5dB
139ms
Enable
12kHz
24kHz
48kHz
−11.5dBV
500µs
512ms
+12dB
0.5dB
0.5dB
128ms
Enable
The following registers should not be changed during the ALC2 operation. These bits should be changed after the ALC2
operation is finished by ALC2 bit is “0” or PMLO bit is “0”.
- LMTHP, LTMP1-0, LMATP1-0, WTMP1-0, RGAINP, REFP5-0, PTS1-0
ALC2=OFF
Exa mple:
Limiter Cycle = 544µs @ fs=44.1kHz
Recovery Cycle = 557ms @ fs= 44.1kHz
Limiter and Recovery Step = 1
Maximum Gain = +12dB
Limiter Detection Level = −11.5dBV
Recovery Transition Time = 139ms @ fs=44.1kHz
ALC2 bit = “1”
WR (LMATP1-0, RGAINP, WT MP1-0)
(1) Addr=12H, Data=18H
WR (LMTHP, LTMP1-0)
WR (REFP5-0)
(2) Addr=13H, Data=18H
(3) Addr=11H, Data=30H
WR (PTS1-0)
WR (ALC2= “1”)
(4) Addr =14H, Data=C0H
(5) Addr=12H, Data=38H
ALC2 Operation
Note : WR : Write
Figure 18. Registers set-up sequence at ALC2 operation
MS0440-E-01
- 30 -
2006/05