AK4665A Datasheet, PDF (36/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
2) ADC (Line In: in case of common jack with headphone)
Power Supply
PDN pin
FS3-0, DFS bits
PMVCM bit
PMCP bit
Clock Input
NVSS pin
(1) >150ns
0H, 0
(2) >0
(3) >0
(4) >0
(5)
Don’t care
0V
XH, X
−HVDD
0H, 0
(10)
Don’t care
0V
PMADC bit
ADC Internal
State
AINL1/R1 pins
SDTO pin
PMHPL/R bits
(6) >0
(8) 2081/fs
PD(Power-down)
Init Cycle
Normal Operation
(7)
(Hi-Z)
(9) GD
(9) GD
PD
(Hi-Z)
(11)
Figure 22. Power-up/down Sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0 and DFS bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set.
(4) PMCP bit should be changed to “1” after PMVCM bit is changed to “1”. The charge pump circuit is powered-up and
NVSS pin goes to –HVDD voltage according to the setting of FS3-0 and DFS bits.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit and ADC.
(6) PMADC bit should be changed to “1” after NVSS pin goes to –HVDD voltage.
(7) When PMADC bit is changed to “1”, AINL1/R1 pins are biased to VCOM voltage. Rising time constant is
determined by input capacitor for AC coupling and input resistance. In case of 1µF input capacitor, time constant is
τ = 1µF x 60kΩ = 60ms (typ)
(8) The analog part of ADC is initialized during 2081/fs (=47ms@fs=44.1kHz) after exiting the power-down state.
SDTO is “L” at that time.
(9) Digital output corresponding to analog input has the group delay (GD) of 17/fs (=385µs@fs=44.1kHz).
(10) When PMCP bit is changed to “0”, the charge pump circuit is powered-down and NVSS pin becomes 0V. Falling
time constant is determined by capacitor and internal resistance (typ 17.5kΩ). In case of 2.2µF capacitor, time
constant is
τ = 2.2µF x 17.5kΩ = 38.5ms (typ)
(11) When PMHPL/R bits = “0”, HPL/R pins are connected to AVSS with internal pull-down resistance (typ 100kΩ).
MS0440-E-01
- 36 -
2006/05