AK4665A Datasheet, PDF (32/52 Pages) Asahi Kasei Microsystems – 20-Bit Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4665A]
„ Headphone Output (HPL/HPR pins)
Power supply voltage for headphone amplifiers is applied from HVDD pin for the positive supply and the negative supply
generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and centered on 0V
(AVSS). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 16Ω. HPG bit set the
output voltage (Table 33).
HPG bit
0
1
Output Voltage
Output Power
1.5Vpp@0dBFS
17mW@16Ω
2.0Vpp@−3dBFS
31mW@16Ω
Table 33. Headphone Output Voltage / Power
Default
The headphone output is enabled when HPMTN bit is “1” and muted when HPMTN bit is “0”. The mute ON/OFF time
are set by PTS1-0 bits (Table 39) when MOFF8 bit is “0”. When MOFF8 bit is “1”, the ON/OFF is done immediately.
When PMHPL and PMHPR bits are “0”, the headphone amplifiers are powered-down completely. At that time, the HPL
and HPR pins are AVSS voltage. The power-up/down time are set by PUT1-0 bits (Table 38) when MOFF0 bit is “0”.
When MOFF0 bit is “1”, the power up/down is done immediately.
PMHPL/R bits
0
1
HPMTN bit
HP-Amp
x
Power-down
0
Power-up & Mute
1
Power-up & Output
Table 34. Headphone output states
Default
The ON/OFF of each path is set by DACHL, LINHL, MINHL, DACHR, RINHR and MINHR bits. The summation gain
of each path is 0dB (typ) at HPG bit = “0” and +5.5dB (typ) at HPG bit = “1”.
LIN/RIN pin
LINHL/RINHR bit
MIN pin
MINHL/MINHR bit
HPL/HP R pin
DACL/DACR
DACHL/DACHR bit
Figure 20. The Summation Circuit of Headphone Output
(L+R)/2 signal of DAC is output from HPL and HPR pins when HPM bit is “1”.
DACHL
HPM bit
HPL pin
0
x
Path OFF
1
0
L
1
(L+R)/2
Table 35. Headphone Output Mode (Lch)
Default
DACHR
HPM bit
HPR pin
0
x
Path OFF
1
0
R
1
(L+R)/2
Table 36. Headphone Output Mode (Rch)
Default
MS0440-E-01
- 32 -
2006/05