AK4688EN Datasheet, PDF (10/36 Pages) Asahi Kasei Microsystems – Asynchronous Stereo CODEC with Capless Line I/O

[AK4688]
Parameter
Symbol
min typ max Unit
Audio Interface Timing (Slave Mode)
PORT2(DAC)
BICK2 Period
tBCK
81
ns
BICK2 Pulse Width Low
tBCKL
20
ns
Pulse Width High
LRCK2 Edge to BICK2 “↑” (Note 13)
BICK2 “↑” to LRCK2 Edge (Note 13)
tBCKH
20
ns
tLRB
20
ns
tBLR
20
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
PORT1 (ADC)
BICK1 Period
tBCK
324
ns
BICK1 Pulse Width Low
tBCKL
128
ns
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 13)
BICK1 “↑” to LRCK1 Edge (Note 13)
tBCKH
128
ns
tLRB
80
ns
tBLR
80
ns
LRCK1 to SDTO (MSB)
BICK1 “↓” to SDTO
tLRS
tBSD
80
ns
80
ns
Audio Interface Timing (Master Mode)
BICK1 Frequency
fBCK
64fs
Hz
BICK1 Duty
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO
Control Interface Timing (I²C Bus):
dBCK
tMBLR
tBSD
50
%
-20
20
ns
20
ns
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
fSCL
-
tBUF
1.3
tHD:STA 0.6
400 kHz
-
μs
-
μs
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 14)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
tLOW
1.3
tHIGH
0.6
tSU:STA
0.6
tHD:DAT
0
tSU:DAT 0.1
tR
-
tF
-
tSU:STO
0.6
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
-
50
ns
Capacitive load on bus
Cb
0
400 pF
Note 13. この規格値はLRCKのエッジとBICKの立ち上がりエッジが重ならないように規定しています。
Note 14. データは最低300ns (SCLの立ち下がり時間) の間保持されなければなりません。
Note 15. I²C-busはNXP B.V.の商標です。
MS1420-J-00
- 10 -
2012/05