AM1705DPTPA3 Datasheet, PDF (7/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
www.ti.com
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
Revision History (continued)
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 5.5
Reset
Section 5.5.1, Power-On Reset (POR):
• Updated/Changed "RTCK is maintained active through a POR." to "RTCK/GP7[14] is maintained active
through a POR."
Section 5.5.2, Warm Reset:
• Updated/Changed “A warm reset provides …” paragraph
• Updated/Changed "RTCK is maintained active through a warm reset." to "RTCK/GP7[14] is maintained
active through a warm reset."
Section 5.8.1.4
AINTC System
Interrupt
Assignments on the
device
Table 5-7, AINTC System Interrupt Assignments:
• Updated/Changed SYSTEM INTERRUPT 27 INTERRUPT NAME from “PROTERR” to
“MPU_BOOTCFG_ERR”
• Updated/Changed SYSTEM INTERRUPT 27 SOURCE from “SYSCFG Protection Shared Interrupt” to
“Shared MPU and SYSCFG Address/Protection Error Interrupt"
Section 5.8.1.5
Table 5-8, AINTC Memory Map:
AINTC Memory Map _{• Deleted "[0]" to 0xFFFE F500 "HIER" REGISTER NAME}
Section 5.11
Section 5.11.2, EMIFA Connection Examples:
External Memory
Interface A (EMIFA) ^{• Added new Subsection}
Section 5.12
Figure 5-17, EMIFB Functional Block Diagram:
External Memory
Interface B (EMIFB) ^{• Added MPU2 block to figure}
Section 5.12.1, EMIFB SDRAM Loading Limitations:
• Moved subsection from Interfacing to SDRAM section to under Section 5.12.1, External Memory
Interface B (EMIFB)
• Updated/Changed “EMIFB supports SDRAM up to 133 MHz …” to “EMIFB supports SDRAM up to 152
MHz …”
Section 5.12.2
Interfacing to
SDRAM
Section 5.12.2, EMIFB Supported SDRAM Configurations:
• Updated/Changed the table to include 8-bit SDRAM Memory Data Bus Width entries
• Updated/Changed "Number of Memories" column from "2" to "1" for the 16-Bit data bus width
Section 5.12.4
EMIFB Electrical
Data/Timing
Table 5-25, EMIFB SDRAM Interface Switching Characteristics:
• Updated/Changed PARAMETER No. 1, t_c(CLK) Cycle time, EMIF clock EMB_CLK MIN value from “7.5”
to “6.579” ns
• Updated/Changed PARAMETER No. 2, t_w(CLK) Pulse width, EMIF clock EMB_CLK high or low MIN
value from “3” to “2.63” ns
Section 5.26.1
Power Domain and
Module Topology
Section 5.26.1.1, Power Domain States:
• Added new subsection
Section 5.29
Section 5.29.1, JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0):
IEEE 1149.1 JTAG _{• Added Silicon Revisions "3.0" and "2.1" to the "0x9B7D F02F for silicon revision 2.0" bullet}
Section 6.1.2
Device and
Development-
Support Tool
Nomenclature
Updated/Changed subsection title from “Device Nomenclature” to “Device and Development-Support Tool
Nomenclature"
Figure 6-1, Device Nomenclature:
• Updated/Changed Silicon Revision to include Revision 3.0
Section 7
Mechanical
Packaging and
Orderable
Information
• Deleted “Mechanical Drawings” section
• Deleted Packaging Materials Information subsection (was Section 7.1 in the previous revision), duplicate
information
• Added Section 7.3, Packaging Information
Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1705
Contents
7