AM1705DPTPA3 Datasheet, PDF (154/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
BIT
31:28
27:12
11-1
0
Table 5-100. JTAG ID Register Selection Bit Descriptions
NAME
VARIANT
PART NUMBER
MANUFACTURER
LSB
Variant (4-Bit) value
Part Number (16-Bit) value
Manufacturer (11-Bit) value
LSB. This bit is read as a "1".
DESCRIPTION
www.ti.com
5.29.2 JTAG Test-Port Electrical Data/Timing
Table 5-101. Timing Requirements for JTAG Test Port (see Figure 5-52)
No.
PARAMETER
MIN
1
t_c(TCK)
Cycle time, TCK
40
2
t_w(TCKH)
Pulse duration, TCK high
16
3
t_w(TCKL)
Pulse duration, TCK low
16
4
t_c(RTCK)
Cycle time, RTCK
40
5
t_w(RTCKH)
Pulse duration, RTCK high
16
6
t_w(RTCKL)
Pulse duration, RTCK low
16
7
t_{su(TDIV-RTCKH)}
Setup time, TDI/TMS/TRST valid before RTCK high
4
8
t_{h(RTCKH-TDIV)}
Hold time, TDI/TMS/TRST valid after RTCK high
4
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Table 5-102. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-52)
No.
9
t_{d(RTCKL-TDOV)}
PARAMETER
Delay time, RTCK low to TDO valid
MIN MAX UNIT
15
ns
TCK
RTCK
2
5
1
4
3
6
TDO
TDI/TMS/TRST
9
8
7
Figure 5-52. JTAG Test-Port Timing
154 Peripheral Information and Electrical Specifications
Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1705