AM1705DPTPA3 Datasheet, PDF (101/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
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SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
Table 5-50. General Timing Requirements for SPI0 Slave Modes⁽¹⁾
No.
9
t_c(SPC)S
10 t_w(SPCH)S
11 t_w(SPCL)S
12 t_{su(SOMI_SPC)S}
13 t_{d(SPC_SOMI)S}
14 t_{oh(SPC_SOMI)S}
15 t_{su(SIMO_SPC)S}
16 t_{ih(SPC_SIMO)S}
PARAMETER
Cycle Time, SPI0_CLK, All Slave Modes
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Setup time, transmit data written to
SPI before initial clock edge from
master.^{(2) (3)}
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Delay, subsequent bits valid on
SPI0_SOMI after transmit edge of
SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Output hold time, SPI0_SOMI valid
afte receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Input Setup Time, SPI0_SIMO valid
before receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Input Hold Time, SPI0_SIMO valid
after receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
MIN
greater of 3P or 40
18
18
2P
MAX
UNIT
ns
ns
ns
2P
ns
2P
2P
18.5
18.5
ns
18.5
18.5
0.5t_c(SPC)S - 3
0.5t_c(SPC)S - 3
ns
0.5t_c(SPC)S - 3
0.5t_c(SPC)S - 3
0
0
ns
0
0
5
5
ns
5
5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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Peripheral Information and Electrical Specifications 101
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