AM1705DPTPA3 Datasheet, PDF (1/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
www.ti.com
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
AM1705 ARM Microprocessor
Check for Samples: AM1705
1 AM1705 ARM Microprocessor
1.1 Features
123
• Highlights
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 128K-Byte RAM Memory
• 3.3V LVCMOS IOs (except for USB Interface)
• Two External Memory Interfaces:
– EMIFA
– Two External Memory Interfaces
• NOR (8-Bit-Wide Data)
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– Two Multichannel Audio Serial Ports
– 10/100 Mb/s Ethernet MAC (EMAC)
– One 64-Bit General-Purpose Timer
• NAND (8-Bit-Wide Data)
– EMIFB
• 16-Bit SDRAM With 128MB Address
Space
• Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
– Autoflow control signals (CTS, RTS) on
UART0 only
– One 64-bit General-Purpose/Watchdog Timer
– Three Enhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• Applications
– Industrial Automation
– Home Automation
– Test and Measurement
– Portable Data Terminals
– Educational Consoles
– Power Protection Systems
• 375/456-MHz ARM926EJ-S™ RISC Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM™Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
• 32-Bit Load/Store RISC architecture
• 4K Byte instruction RAM per core
• 512 Bytes data RAM per core
• PRU Subsystem (PRUSS) can be disabled
via software to save power
– Standard power management mechanism
• Clock gating
• Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• Two Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 Full-Speed Client
– USB 2.0 Full-/Low-Speed Host
– End Point 0 (Control)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM926EJ-S, ETM9, CoreSight are trademarks of ARM Limited.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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