AM1705DPTPA3 Datasheet, PDF (67/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
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SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
5.12 External Memory Interface B (EMIFB)
The following EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as an overbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters.
EMIFB
CPU
EDMA
Master
Peripherals
Crossbar
MPU2
Registers
EMB_CS
EMB_CAS
Cmd/Write
FIFO
EMB_RAS
EMB_WE
EMB_CLK
Read
FIFO
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
EMB_D[x:0]
EMB_WE_DQM[x:0]
SDRAM
Interface
Figure 5-17. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
5.12.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
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Peripheral Information and Electrical Specifications
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