AM1705DPTPA3 Datasheet, PDF (157/164 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
www.ti.com
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
7 Mechanical Packaging and Orderable Information
This section describes the device orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
7.1 Thermal Data for PTP
The following table(s) show the thermal resistance characteristics for the PowerPAD^TM PTP mechanical
package.
Table 7-1. Thermal Resistance Characteristics (PowerPAD^TM Package) [PTP]"
No.
1 RΘ_JC
2 RΘ_JB
3 RΘ_JA
4
Junction-to-case
Junction-to-board
Junction-to-free air
5
6 ^{RΘJMA Junction-to-moving air}
7
8
9
10 Psi_JT
11
Junction-to-package top
12
13
14
15 Psi_JB
16
Junction-to-board
17
°C/W ⁽¹⁾
7.8
6.2
21.3
14.3
13.1
12.1
11.2
0.5
0.6
0.7
0.8
1.0
6.3
5.9
5.9
5.8
5.8
°C/W ⁽²⁾
9.4
9.9
27.9
20.2
18.6
17.4
16.2
0.7
0.9
1.0
1.1
1.3
9.5
8.8
8.7
8.6
8.5
°C/W ⁽³⁾
8.6
7.1
23.2
°C/W ⁽⁴⁾
10.1
10.6
30.6
22.6
21.0
19.6
18.2
0.8
1.0
1.1
1.3
1.5
10.8
9.9
9.8
9.7
9.6
AIR FLOW
(m/s) ⁽⁵⁾
N/A
N/A
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers
connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 1oz (35um) top and bottom.
(5) m/s = meters per second
7.2 Supplementary Information About the 176-pin PTP PowerPAD™ Package
This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas
Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002)
should be consulted when creating a PCB footprint for this device.
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Mechanical Packaging and Orderable Information 157
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