Z87200 Datasheet, PDF (6/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Z87200
Spread-Spectrum Transceiver
PIN DESCRIPTION (Continued)
Table 1. 100-Pin PQFP Pin Description
No
Symbol
Function
1,11,31,40,51,6 V
5,75,81,90
DD
2
RXQIN0
3
RXQIN1
4
RXQIN2
5
RXQIN3
6
RXQIN4
7
RXQIN5
8
RXQIN6
9
RXQIN7
10
RXXE
12
RXIFCLK
13,15,30,39,50, V
64,74,80,89
SS
14
TXIFCLK
16
/RESET
17
MTXE
18
TXIN
19
TXMCHP
20
DATA0
21
DATA1
22
DATA2
23
DATA3
24
DATA4
25
DATA5
26
DATA6
27
DATA7
28
/WR
29
/CSEL
32
ADDR0
33
ADDR1
34
ADDR2
35
ADDR3
36
ADDR4
37
ADDR5
38
ADDR6
41
RXTEST7
42
RXTEST6
43
RXTEST5
44
RXTEST4
45
RXTEST3
46
RXTEST2
47
RXTEST1
48
RXTEST0
49
/OEN
52
RXSYMPLS
53
RXSPLPLS
Power Supply
Rx Q-Channel Input
(Bit 0; LSB)
Rx Q-Channel Input (Bit 1)
Rx Q-Channel Input (Bit 2)
Rx Q-Channel Input (Bit 3)
Rx Q-Channel Input (Bit 4)
Rx Q-Channel Input (Bit 5)
Rx Q-Channel Input (Bit 6)
Rx Q-Channel Input
(Bit 7; MSB)
Manual Receiver Enable
Receiver I.F. Clock
Ground
Transmitter I.F. Clock
/Reset
Manual Transmitter Enable
Transmitter Input
Transmitter Manual Chip Pulse
Data Bus (Bit 0; LSB)
Data Bus (Bit 1)
Data Bus (Bit 2)
Data Bus (Bit 3)
Data Bus (Bit 4)
Data Bus (Bit 5)
Data Bus (Bit 6)
Data Bus (Bit 7; MSB)
Write Bar
Chip Select Bar
Address Bus (Bit 0; LSB)
Address Bus (Bit 1)
Address Bus (Bit 2)
Address Bus (Bit 3)
Address Bus (Bit 4)
Address Bus (Bit 5)
Address Bus (Bit 6; MSB)
Receiver Test Output (Bit 7)
Receiver Test Output (Bit 6)
Receiver Test Output (Bit 5)
Receiver Test Output (Bit 4)
Receiver Test Output (Bit 3)
Receiver Test Output (Bit 2)
Receiver Test Output (Bit 1)
Receiver Test Output (Bit 0)
Output Enable Bar
Receiver Symbol Pulse
Receiver Sample Pulse
Zilog
Table 1. 100-Pin PQFP Pin Description
No
Symbol
Function
54
55
56
57
58
59
60
61
62
63
66
67
68
69
70
71
72
73
76
77
78
79,82
83
84
85
86
87
88
91
92
93
94
95
96
97
98
99
100
/RXDRDY
RXQOUT
RXIOUT
RXOUT
I.C.
TXTEST
TXACQPLS
TXTRKPLS
TXCHPPLS
TXBITPLS
TXIFOUT7
TXIFOUT6
TXIFOUT5
TXIFOUT4
TXIFOUT3
TXIFOUT2
TXIFOUT1
TXIFOUT0
TXQOUT
TXIOUT
TXACTIVE
N.C.
RXACTIVE
RXMSMPL
MFLD
MNCOEN
RXMABRT
RXMDET
RXIIN0
RXIIN1
RXIIN2
RXIIN3
RXIIN4
RXIIN5
RXIIN6
RXIIN7
N.C.
V
SS
Receiver Data Ready Bar
Receiver Q Channel Output
Receiver I Channel Output
Receiver Output
[Note]
Transmitter Test Output
Transmitter Acquisition Pulse
Transmitter Data Track Pulse
Transmitter Chip Pulse
Transmitter Bit Pulse
Tx I.F. Output (Bit 7, MSB)
Tx I.F. Output (Bit 6)
Tx I.F. Output (Bit 5)
Tx I.F. Output (Bit 4)
Tx I.F. Output (Bit 3)
Tx I.F. Output (Bit 2)
Tx I.F. Output (Bit 1)
Tx I.F. Output (Bit 0, LSB)
Tx Q-Channel Output
Tx I-Channel Output
Transmitter Active
No Connection
Receiver Active
Receiver Manual Sample Clock
Manual Frequency Load
Manual NCO Enable
Receiver Manual Abort
Receiver Manual Detect
Rx I-Channel Input
(Bit 0; LSB)
Rx I-Channel Input (Bit 1)
Rx I-Channel Input (Bit 2)
Rx I-Channel Input (Bit 3)
Rx I-Channel Input (Bit 4)
Rx I-Channel Input (Bit 5)
Rx I-Channel Input (Bit 6)
Rx I-Channel Input (
Bit 7; MSB)
No Connection
Ground
Note: I.C. denotes Internal Connection. Do not use for vias.
4-6
DS96WRL0400