Z87200 Datasheet, PDF (23/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Zilog
Z87200
Spread-Spectrum Transceiver
NCO. Note that MNCOEN operates independently of MTXEN and MNCOEN, where these signals have similar
MTXEN and MRXEN, where those pins have similar con- control over the transmit and NCO circuitry, respectively.
trol over the transmit and receive circuitry, respectively.
4 ^{MRXEN performs the same function as bit 2 of address}
MNCOEN performs the same function as bit 0 of address 37_H, and these two signals are logically ORed together to
37_H, and these two signals are logically ORed together to form the overall control function. When bit 2 of address 37_H
form the overall control function. When bit 0 of address 37_H is set low, MRXEN controls the activity of the receiver cir-
is set low, MNCOEN controls the activity of the NCO cir- cuitry and, when MRXEN is set low, bit 2 of address 37_H
cuitry; when MNCOEN is set low, bit 0 of address 37_H con- controls the activity of the receiver circuitry. When either
trols the activity of the NCO circuitry. When either bit 0 or MRXEN or bit 2 (whichever is in control, as defined above)
MNCOEN (whichever is in control, as defined above) goes goes low, a reset sequence begins on the following RXIF-
low, a reset sequence occurs on the following RXIFCLK CLK cycle and continues through a total of six RXIFCLK
cycle to effectively disable all of the NCO circuitry, al- cycles to virtually disable all of the receiver data paths. The
though the user programmable control registers are not af- user-programmable control registers are not affected by
fected by this power down sequence.
the power-down sequence, with the exception of
Upon reactivation (when either MNCOEN or bit 0 of ad-
dress 37_H return high), the NCO must be reloaded with fre-
quency control information either by means of the MFLD
input or by writing 01_H into address 00_H.
RXTEST_7-0 Function Select (address 38_H), which is reset
to 0. If the RXTEST_7-0 bus is being used to read any func-
tion other than the PN Matched Filter I and Q inputs, the
value required must be rewritten after re-enabling the re-
ceiver.
MTXEN (Pin 17)
Manual Transmitter Enable. A rising edge on MTXEN
causes the transmit sequence to begin, where the Z87200
first transmits a single Acquisition/Preamble symbol fol-
lowed by data symbols. MTXEN should be set low after the
last symbol has been transmitted. When MTXEN is set
low, power consumption of the transmitter circuit is mini-
mized. MTXEN operates independently of MRXEN and
MNCOEN, where these signals have similar control over
the receive and NCO circuitry, respectively.
MTXEN performs the same function as bit 1 of address
37_H. and these two signals are logically ORed together to
form the overall control function. When bit 1 of address 37_H
is set low, MTXEN controls the activity of the transmitter
circuitry, and, when MTXEN is set low, bit 1 of address 37H
controls the activity of the transmitter circuitry. A rising
edge on either MTXEN or bit 1 (whichever is in control, as
defined above) initiates a transmit sequence. A falling
edge initiates a reset sequence on the following TXIFCLK
cycle to disable all of the transmitter data path, although
the user programmable control registers are not affected
by the power down sequence.
MRXEN (Pin 10)
Manual Receiver Enable. MRXEN allows power con-
sumption of the Z87200 receiver circuitry to be minimized
when the device is not receiving. With the instantaneous
acquisition properties of the PN Matched Filter, it is often
desirable to shut down the receiver circuitry to reduce pow-
er consumption, resuming reception periodically until an
Acquisition/Preamble symbol is acquired. Setting MRXEN
low reduces the power consumption substantially. When
MRXEN is set high, the receiver will automatically power
up in acquisition mode regardless of its prior state when it
was powered down. MRXEN operates independently of
TXIN (Pin 18)
Transmit Input. TXIN supports input of the information
data to be transmitted by the Z87200. In BPSK mode, the
transmitter requires one bit per symbol period; in QPSK
mode, two bits are required per symbol period.
To initiate and enable transmission of the data, the user
must raise MTXEN high. Data for transmission is request-
ed with TXBITPLS, where one or two pulses per symbol
are generated depending on whether the device is in
BPSK or QPSK mode as set by bit 0 of address 40_H. To al-
low monitoring of the state of the transmitter, the Z87200
will pulse TXACQPLS after the initial Acquisition/Preamble
symbol is transmitted; the transmission of each subse-
quent symbol is indicated by pulses of TXTRKPLS.
If programmed for BPSK mode, data is requested by the
Z87200 by a rising edge of output signal TXBITPLS, where
TKBITPLS is generated once per symbol, one chip period
before the end of the current symbol. At the end of the sym-
bol duration, the TXIN data is latched into the device. TX-
BITPLS falls low immediately following the rising edge of
TXIFCLK, which latches the TXIN value, and is generated
repeatedly at the symbol rate as long as the input signal
MTXEN remains high.
In QPSK mode, data is requested by the Z87200 by a ris-
ing edge of output signal TXBITPLS, where this signal is
generated twice per symbol, first one chip period before
the middle of the symbol and then one chip period before
the end of the symbol. TXBITPLS requests the data exact-
ly one chip cycle before latching the TXIN data into the de-
vice. TXBITPLS falls low immediately following the rising
edge of TXIFCLK, which latches the TXIN value.
DS96WRL0400
4-23